Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Finding and fixing double patterning problems in 20nm designs
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
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