A look at the USB 3.0 physical layer, including the PHY and the physical connection between two ports, which is carried on two differential data pairs.
The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
The growing verification challenge, and how to address it by coordinating multiple debug strategies.
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
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