Synopsys

January 24, 2013
Neill Mullinger, group marketing manager for VIP, Synopsys

Verification IP: the questions you should ask

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
December 12, 2012
Xilinx 3D-IC interposer featured image

Enabling 3D-IC design

Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
December 6, 2012

20nm timing analysis – a practical and scalable approach

Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
November 16, 2012
Synopsys Virtualizer screen shot

The Shift Left: how virtual prototyping reduces risk

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
November 16, 2012
Marco Casale-Rossi

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , , ,
November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: , ,
October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:
October 9, 2012
tdf-oct12-snps20pv-feat

Physical verification of 20nm designs through integrated double-patterning analysis and repair

Finding and fixing double patterning problems in 20nm designs
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
September 12, 2012
tdf-sept-SNPS-crit-tools-feat

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
September 6, 2012
Antun Domic

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:

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