Synopsys

February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
January 15, 2014
Featured image for Debugging with VPs - III

Debugging with virtual prototypes – Part Three

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
January 7, 2014
Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.

Using HAPS to streamline IP to SoC integration

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - IC Implementation  |  Tags: , ,   |  Organizations:
December 16, 2013
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
December 8, 2013

Debugging with virtual prototypes – Part Two

The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
November 6, 2013

Improving performance through better delay estimation of sub-32nm interconnects

Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
October 23, 2013

FPGA-based prototyping to validate the integration of IP into an SoC

A case study describing validation of the integration of USB3.0 and USB2.0 interface IP that illustrates broader challenges FPGA-based prototyping presents.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations:
September 24, 2013

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
September 17, 2013

Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design

Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:

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