The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
A case study describing validation of the integration of USB3.0 and USB2.0 interface IP that illustrates broader challenges FPGA-based prototyping presents.
How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
The first of a series of seven articles describing the key details of the USB 3.0 protocol.
A look at the way in which the USB 3.0 Link Layer manages the port-to-port flow of data between the host and the device.
An overview of the USB 3.0 architecture, covering the USB Host, USB Device(s) and USB Interconnect, as well as the related receptacles, plugs and cables.
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