Synopsys

September 16, 2013

The USB 3.0 Link Layer

A look at the way in which the USB 3.0 Link Layer manages the port-to-port flow of data between the host and the device.
Article  |  Topics: IP - Assembly & Integration  |  Tags: ,   |  Organizations:
September 16, 2013

USB 3.0 system overview

An overview of the USB 3.0 architecture, covering the USB Host, USB Device(s) and USB Interconnect, as well as the related receptacles, plugs and cables.
Article  |  Topics: IP - Assembly & Integration  |  Tags: ,   |  Organizations:
September 16, 2013

USB 3.0 protocol layer – part 1

A first look at the role of the protocol layer in USB 3.0.
Article  |  Topics: IP - Assembly & Integration  |  Tags: , ,   |  Organizations:
September 16, 2013
SuperSpeed_USBLogo - feat

The USB 3.0 Functional Layer

A look at the USB 3.0 functional layer, an application layer and system software on the host side, and a logical function and device on the device side.
Article  |  Topics: IP - Assembly & Integration  |  Tags: , ,   |  Organizations:
September 16, 2013

USB 3.0 protocol layer – part 2

A look at the role of four types of transaction in the USB 3.0 protocol layer: bulk, control, interrupt and isochronous.
Article  |  Topics: IP - Assembly & Integration  |  Tags: , ,   |  Organizations:
September 16, 2013

The USB 3.0 Physical Layer

A look at the USB 3.0 physical layer, including the PHY and the physical connection between two ports, which is carried on two differential data pairs.
Article  |  Topics: IP - Assembly & Integration  |  Tags: ,   |  Organizations:
September 10, 2013
embeddebug_feat img

Debugging with virtual prototypes – Part One

The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: ,   |  Organizations: , , ,
September 3, 2013
SNPS TDF UPF hierarchy feat img

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
August 12, 2013
Steve Smith of Synopsys

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,

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