Synopsys

July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
July 9, 2014
Car cutaway

Using Ethernet in automotive networks

Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , , , , ,   |  Organizations:
June 27, 2014
M-PCIe_fig1

How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe

How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
Article  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , , , ,   |  Organizations:
May 24, 2014
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Expert Insight  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , ,   |  Organizations:
April 28, 2014
Synopsys RC HS story featured image

Overcoming the power/performance paradox in processor IP

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
March 24, 2014
HAPS-DX

Prototyping solutions for validation of complex ASIC IP

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations: ,
February 26, 2014
Synopsys VCS Xprop feat

Catching X-propagation related issues at RTL

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification
Article  |  Topics: EDA - Verification  |  Tags:   |  Organizations:
February 11, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.

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