ST Microelectronics

September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
May 23, 2016
Road signs used to train IDSIA neural network

Bit width tweaks point way to practical deep learning

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.
May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
January 30, 2015

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: , ,
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,

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