Samsung Electronics

October 3, 2016
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

Wally Rhines separates the signal from the noise

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
January 31, 2013
Balance image for Cadence AVIP article

Accelerated VIP solves firmware and driver integration and validation tradeoffs

Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.
November 16, 2012
Marco Casale-Rossi

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , , ,

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