Reset optimization pays big dividends before simulation
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Real Intent
Hierarchy provides a smarter approach to SoC CDC verification
Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Complexity drives smart reporting
Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
A common methodology to manage X propagation in both design and verification
How all types of engineer can focus on X states that represent real risk, and set aside those that are artifacts of a design process.
The challenge of clock domain crossings – and some solutions
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Building an RTL sign-off flow
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Better analysis helps improve design quality
Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Clock-domain and reset verification in the low-power design era
The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
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