Real Intent

February 29, 2016
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

How to expose X-optimism issues in ASIC and FPGA design

Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
January 26, 2016
Bus contention and floating bus issues featured image

Bus contention and floating busses: Catch them before simulation

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
January 18, 2016
How to debug and verify finite state machines early in the design flow

Finite state machines: How to debug and verify them early in the flow

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
December 16, 2015
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

Fix X-pessimism in netlists with practical techniques

Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.
May 31, 2015

Technology trends demand netlist-level CDC verification

Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
May 11, 2015

Verifying clock domain crossings when using fast-to-slow clocks

A look at three techniques to verify the validity of signals moving between clock domains
February 25, 2015
Pranav Ashar

DO-254 without tears

Compliance with aviation’s hardware design standard is seen as a ‘tough ask’, but EDA’s own evolution has made that process easier than you may think.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
January 13, 2015
Sarath Kirihennedige, Real Intent

Taking control of constraints verification

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
Expert Insight  |  Topics: Uncategorized  |  Tags: , , , ,   |  Organizations:
September 30, 2014
Pranav Ashar

The evolution of lint

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

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