ProPlus Design Solutions

October 28, 2015
Bruce McGaughy, CTO, ProPlus Design Solutions

FastSPICE simulators hit their expiration date

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
May 30, 2014

How the right DFY flow enhances performance and profit

'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , , ,   |  Organizations:

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