Mentor

January 16, 2019
Virtual sequences with portable stimulus - featured image.

Create more flexible virtual sequences with Portable Stimulus

Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
December 31, 2018
MBH featured image

Enhanced model-based hinting may be the edge you need below 20nm

A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Article  |  Topics: EDA - DFM  |  Tags: , , , , , ,   |  Organizations: , , , ,
December 11, 2018

Win on the fault campaign trail with formal

How formal verification for the ISO26262 automotive functional safety delivers the full activation, propagation, and observation in the form of proven and exhaustive results.
November 20, 2018
HDAP_FeaturedImage

Adding system-level, post-layout electrical analysis to HDAP design and verification

Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , ,   |  Organizations: , ,
October 16, 2018
Reliability verification feature - featured image

Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations:
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
September 20, 2018
SSD controller case study featured image

How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
Article  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations: ,
September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,
August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , , , , ,   |  Organizations:
July 9, 2018
Channel sharing and hierarchical DFT - Featured Image

Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:

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