Mentor

October 16, 2018
Reliability verification feature - featured image

Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations:
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
September 20, 2018
SSD controller case study featured image

How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
Article  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations: ,
September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,
August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , , , , ,   |  Organizations:
July 9, 2018
Channel sharing and hierarchical DFT - Featured Image

Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
June 18, 2018

Formal fault analysis for ISO 26262: Find faults before they find you

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
June 11, 2018

How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
May 9, 2018

Extend formal property verification to protocol-driven datapaths

Learn how planning and upfront knowledge of the challenges ahead can open up what has seemed a challenging task.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
April 23, 2018
data validation featured image

The three critical data validation points in a design flow

Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Article  |  Topics: IP - Design Management, EDA - DFM, Verification  |  Tags: , , , , , , , ,   |  Organizations:

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