Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Early use of design for manufacturing can capture PCB yield issues related to pads, copper distribution, same net slivers and more
Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
Characterizing standard-cell defect mechanisms helps improve IC testing
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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