Mentor Graphics

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.

The Linux Trace Tookit next generation provides open source tracer technology that helps surmount debug and optimization challenges

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.

Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.

Early use of design for manufacturing can capture PCB yield issues related to pads, copper distribution, same net slivers and more

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.

Characterizing standard-cell defect mechanisms helps improve IC testing