Mentor Graphics

November 13, 2012
Anil Khanna

Embedded systems are evolving, but where are the tools?

Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
Expert Insight  |  Topics: Embedded - Architecture & Design, Integration & Debug  |  Tags: ,   |  Organizations:
October 26, 2012

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Article  |  Topics: EDA Topics, EDA - ESL, Verification  |  Tags: , , , ,   |  Organizations:
October 23, 2012
A same net sliver

Better PCB design using the fabricator’s view

Early use of design for manufacturing can capture PCB yield issues related to pads, copper distribution, same net slivers and more
September 14, 2012

Moving to advanced reliability verification

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
August 18, 2012

When good DFT goes bad: debugging broken scan chains

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
July 26, 2012
tdf-jul12-mentor-foster-fig 1-feat

Synthesizing assertions into hardware for faster silicon debug

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
July 3, 2012
Juergen Schloeffel

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
Expert Insight  |  Topics: EDA - DFT  |  Tags: , , ,   |  Organizations:
June 1, 2012
Michael Buehler-Garcia

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:
May 22, 2012
Jeff Wilson

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Expert Insight  |  Topics: EDA - DFM  |  Tags: ,   |  Organizations:
May 22, 2012

Effective finger-pointing: the art of modern yield analysis

Correlating production test failure diagnosis with DFM analysis can help identify and understand systematic yield issues, and to find out whether they are linked to DFM violations.
Article  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:


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