Mentor Graphics

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?

The encryption chain for today's highly collaborative designs needs to be managed with care.

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.

Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.

Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?