May 13, 2016
A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
April 26, 2016
These days, when it comes to innovation: The car's the star - not the stooge.
March 21, 2016
New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
March 3, 2016
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
February 18, 2016
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
February 11, 2016
Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
January 27, 2016
What can you add to a challenging project without pushing out deadlines and muddling communication?
January 22, 2016
How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
January 11, 2016
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
January 4, 2016
Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.