Mentor Graphics

July 22, 2016
Dr Lauro Rizzatti, verification consultant

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
July 15, 2016
Hans van der Schoot is a methodologist in the Emulation division of Mentor Graphics

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
May 13, 2016
Jenkins automation server logo

How continuous integration with Jenkins serves verification flows

A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
Article  |  Topics: Uncategorized, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
April 26, 2016
Andrew Macleod is Director of Automotive Marketing for Mentor Graphics. He has more than 15 years of experience in the automotive software and semiconductor industry, with expertise in new product development and introduction, product management and global strategy, including a focus on the Chinese auto industry.

Still using Moore’s Law to beat up on the automotive industry?

These days, when it comes to innovation: The car's the star - not the stooge.
Expert Insight  |  Topics: EDA - IC Implementation, Embedded - Platforms  |  Tags: , , , ,   |  Organizations:
March 21, 2016
featimrtlsynth

How to maximize productivity with faster, high-capacity RTL synthesis

New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
Article  |  Topics: Uncategorized  |  Tags: , ,   |  Organizations:
March 3, 2016
Whats cooking at the Flash Diner - verification IP

What’s cooking at the Flash Diner?

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
February 11, 2016
David Wiens is Business Development Manager for the System Design Division at Mentor Graphics.

Where tools end and best practices begin

Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
January 27, 2016
Dr Lauro Rizzatti, verification consultant

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?

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