Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
The encryption chain for today's highly collaborative designs needs to be managed with care.
Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.
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