Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
What can you add to a challenging project without pushing out deadlines and muddling communication?
How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
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