Mentor Graphics

November 8, 2016
Technical feature on scan pattern best practice

Best practice in scan pattern ordering for test and diagnosis

How to tune your scan pattern creation and application to cost-effectively match your test objectives.
Article  |  Topics: EDA - DFT  |  Tags: , , , , ,   |  Organizations:
October 14, 2016
networking-soc-mentor-ixia-featim

Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
Article  |  Topics: EDA - DFT, - Uncategorized, EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
October 3, 2016
Dr Walden Rhines is Chairman and CEO of Mentor Graphics

Wally Rhines separates the signal from the noise

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
September 9, 2016
Jean-Marie Brunet is Senior Director of Marketing for the Emulation Division at Mentor Graphics.

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
August 12, 2016
Phil Brumby is a Senior Technical Marketing Engineer in the Mentor Graphics Embedded Systems Division.

How to analyze embedded GUI performance effectively

Users now demand a smooth GUI experience. Making sure they get one requires harvesting and understanding key metrics.
July 22, 2016
Dr Lauro Rizzatti, verification consultant

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
July 15, 2016
Hans van der Schoot is a methodologist in the Emulation division of Mentor Graphics

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
May 13, 2016
Jenkins automation server logo

How continuous integration with Jenkins serves verification flows

A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
Article  |  Topics: Uncategorized, EDA - Verification  |  Tags: , , ,   |  Organizations: ,

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