The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
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