Mentor Graphics

January 19, 2017
USB Type-C VIP featured image

USB Type-C: Verification challenges and solutions

The USB Type-C connector is versatile and already gaining traction in laptops, tablets and desktops. Here's how verification IP plays an important role in achieving the best implementation.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations:
January 10, 2017
Silicon bring-up Tessent

Accelerate silicon bring-up in a bench-top environment

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
Article  |  Topics: EDA - DFT, - EDA Topics  |  Tags: , ,   |  Organizations: ,
December 29, 2016
Danit Atar is a senior marketing programs specialist at Mentor Graphics

A reliability checklist for the Connected World

Reliability is growing to match security as a key challenge for PCB design. These tools and techniques will help you rise to it.
December 20, 2016
NVMe VIP featured image

Nine effective features of NVMe VIP for SSD storage

The open NVMe standard is helping non-volatile memory storage reach its true potential with increasingly rich verification support
Article  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
December 9, 2016
Featured image - analog design constraints

A new path for analog design constraints verification

Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
December 7, 2016
David Wiens is Business Development Manager for the System Design Division at Mentor Graphics.

Tackling the multi-board reality of systems of systems

We talk to Mentor's David Wiens about how the company is giving the board-to-factory design flow a needed upgrade.
Expert Insight  |  Topics: Uncategorized  |  Tags: , , , , , , , , ,   |  Organizations:
November 8, 2016
Technical feature on scan pattern best practice

Best practice in scan pattern ordering for test and diagnosis

How to tune your scan pattern creation and application to cost-effectively match your test objectives.
Article  |  Topics: EDA - DFT  |  Tags: , , , , ,   |  Organizations:
October 14, 2016
networking-soc-mentor-ixia-featim

Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
Article  |  Topics: EDA - DFT, - Uncategorized, EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
October 3, 2016
Dr Walden Rhines is Chairman and CEO of Mentor Graphics

Wally Rhines separates the signal from the noise

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.

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