John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
How EDA tools are evolving to make it possible to design with finFET processes.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
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