IEEE

June 20, 2018

Bringing Ethernet time-sensitive networking to automotive applications

An evolution of the Ethernet standard enable time-sensitive networking with the predictable latencies and guaranteed bandwidth necessary for automotive applications.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations: ,
October 18, 2017
Channel Operating Margin featured image

How Channel Operating Margin helps Gigabit Ethernet PCB analysis

The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Article  |  Topics: PCB - Design Integrity, - PCB Topics  |  Tags: , , , , , , , ,   |  Organizations: ,
May 9, 2017
John Swanson John Swanson is senior marketing manager for DesignWare IP at Synopsys.

Building faster data centers with 25G Ethernet

The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations: ,
November 22, 2016
Visual: cars speeding along a road

Implementing DDR DRAM in automotive applications

A look at how DDR DRAM is being adapted for use in automotive systems, and the demands its use puts upon interface IP for SoCs.
Article  |  Topics: IP Topics, IP - Selection  |  Tags: , , , , ,   |  Organizations: ,
October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Expert Insight  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , ,   |  Organizations: ,
August 5, 2015
Power switch

‘Even the software guys are starting to talk in milliwatts’

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
June 25, 2015

Applying agile techniques to IC design

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
November 11, 2013
Brian Fuller is editor in chief at Cadence Design Systems.

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,
February 25, 2011

The fast run

DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.
Article  |  Topics: EDA - IC Implementation  |  Tags:   |  Organizations:

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