The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
A look at how DDR DRAM is being adapted for use in automotive systems, and the demands its use puts upon interface IP for SoCs.
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.
Europe’s premier EDA conference moves to Silicon Saxony
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