EDA

How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.

Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.

How EDA tools are evolving to make it possible to design with finFET processes.

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages

This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.

A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.