Verifying clock domain crossings when using fast-to-slow clocks
A look at three techniques to verify the validity of signals moving between clock domains
EDA
Fixing late ECOs in ARM core subsystems at STMicroelectronics
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
Achieving safety and security in SoC development
Designers will have to update development processes to achieve the rigorous safety certifications required in automotive, rail, avionics and similar markets
Putting emulation on the map
Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Developing and integrating configurable GPU IP using FPGA-based prototyping
How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
Layout automation and simulation support DDR4 at lower system cost
The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.
A better method for early and accurate power estimation
Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
A review of model development for 10nm lithography
John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
Design reaches out from the edge
We are moving towards a "continuum of compute", ARM CEO Simon Segars said at CDNLive Silicon Valley, a trend that will reshape design.
Getting the most out of IP based FPGA design with Synplify
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
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