EDA

October 16, 2018
Reliability verification feature - featured image

Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations:
October 16, 2018
Dana Neustadter is a senior manager of product marketing for Synopsys’ Security IP solutions.

Why AI needs security

As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
Expert Insight  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
October 9, 2018

Using threat models and risk assessments to define device security requirements

The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations:
October 5, 2018
Gate-level simulation feature

How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
October 3, 2018
Allen Watson of Synopsys

An open-source framework for greater flexibility in machine-learning development

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Expert Insight  |  Topics: Embedded - Architecture & Design, EDA - ESL  |  Tags: , , ,   |  Organizations: , , , , ,
September 23, 2018
Gordon Cooper

Flexible embedded vision processing architectures for machine-learning applications

Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations:
September 20, 2018
SSD controller case study featured image

How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
Article  |  Topics: EDA - Verification  |  Tags: , , , , , ,   |  Organizations: ,
September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,
August 14, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , , , , ,   |  Organizations:

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