EDA

July 23, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

The budget case for formal verification

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
July 11, 2018
Ruud Derwig has more than 20 years of experience with software and system architectures for embedded systems. Key areas of expertise include (real-time, multi-core) operating systems, media processing, component based architectures, and security. He holds a master's degree in computing science and a professional doctorate in engineering. Derwig is currently a software and systems architect at Synopsys.

Picking the right-sized crypto processor for your SoC

Choosing the right crypto processor implementation involves a complex set of design tradeoffs between speed, area, power consumption and flexibility. Using consistent benchmarks can help explore your options.
Expert Insight  |  Topics: IP Topics, IP - Selection  |  Tags: , , , ,   |  Organizations: ,
July 9, 2018
Channel sharing and hierarchical DFT - Featured Image

Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
June 20, 2018

Bringing Ethernet time-sensitive networking to automotive applications

An evolution of the Ethernet standard enable time-sensitive networking with the predictable latencies and guaranteed bandwidth necessary for automotive applications.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations: ,
June 18, 2018

Formal fault analysis for ISO 26262: Find faults before they find you

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
June 18, 2018
Andy Ladd is president and CEO of Baum. He has more than 30 years of experience in the electronics industry. Ladd received a Bachelor of Science degree in Computer Engineering from the University of Illinois at Champaign/Urbana, and a Master of Science degree in Engineering from the University of Michigan at Ann Arbor.

Power analysis isn’t just for battery-operated products

Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
June 11, 2018

How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.
May 31, 2018
layout file feature

Layout-database file control: the missing link

The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , , , ,   |  Organizations:
May 24, 2018
Gordon Cooper

The impact of AI on autonomous vehicles

Many car manufacturers are exploring the possibilities of autonomous vehicles. But what will it take to build sufficient AI performance into them to enable true autonomy?
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations: ,
May 9, 2018

Extend formal property verification to protocol-driven datapaths

Learn how planning and upfront knowledge of the challenges ahead can open up what has seemed a challenging task.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:

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