Chipmaker

The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.

Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.

Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.

OpenCL aims to open up the performance of graphics processors to other applications. It is also one more way in which compilation is being moved to runtime to make it easier to move code dynamically across heterogeneous platforms.