Chipmaker

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?

The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.