Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
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