Increasing resolutions and rising frame rates are making it more challenging than ever to drive embedded displays effectively.
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
How to combine a display processing unit from one company and a MIPI Display Serial Interface solution from another to build 4K embedded displays for smartphones and AR/VR devices.
Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
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