Chipmaker

January 9, 2018
HBM article featimg

Choosing between DDR4 and HBM in memory-intensive applications

Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations: , , ,
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 30, 2017
Debug case study for ARM/AXI based design

Case study: Verifying and optimizing software for power on SoCs

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
September 21, 2017
Diagnosis-driven yield analysis featured image

Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
September 8, 2017
Ultra D HLS featured image

How HLS is giving shape to glasses-free 3DTV

High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
May 22, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
May 15, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part Two: AI, automotive and security

This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , , , , , , ,   |  Organizations: , , ,
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon中国将于4月在上海亮相

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。
Article  |  Topics: Uncategorized  |  Tags: , , , , , , ,   |  Organizations: , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors