August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
November 6, 2013

Improving performance through better delay estimation of sub-32nm interconnects

Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes


Synopsys Cadence Design Systems Mentor - A Siemens Business
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