Cadence Design Systems

October 27, 2013
Richard Goering, senior manager of technical communications, Cadence

IPC-2581 transfer standard gains momentum

Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.
Expert Insight  |  Topics: PCB - System Codesign  |  Tags: ,   |  Organizations:
October 11, 2013
Axel Scherer is a solutions architect at Cadence Design Systems in Massachusetts, leading the Incisive Product Expert Team for testbenches in general and the Universal Verification Methodology (UVM) in particular.

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
October 8, 2013
Cadence EAD flow

End mixed-signal infinite loops with electrically aware design

Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
September 24, 2013
Hybrid memory cube architecture

DRAM interfaces for mobile and networking designs

Mobile and networking platforms need high bandwidth, low power consumption, and small footprint. These needs drove standards, such as LPDDR4, Wide I/O 2 and Hybrid Memory Cube.
Article  |  Topics: IP - Selection  |  Tags: , , , , , , ,   |  Organizations:
September 6, 2013
Richard Goering, senior manager of technical communications, Cadence

Real-world multicore embedded systems: review

If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.
May 8, 2013
3D-IC cross-section

Eight requirements for 3D-IC design

Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
April 10, 2013
Richard Goering, senior manager of technical communications, Cadence

Focus on product creation for effective design

An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
January 31, 2013
Balance image for Cadence AVIP article

Accelerated VIP solves firmware and driver integration and validation tradeoffs

Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.
October 30, 2012
Mixed-Signal Methodology Guide

Verifying low-power intent in mixed-signal design

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Article  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations: ,

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