FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Cadence Design Systems
A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.
Decoupling capacitor counts are increasing as PCBs deploy more advanced silicon. But you can use automated analysis to bring counts and costs under control.
Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
View All Sponsors