Cadence Design Systems

August 7, 2014
Hitendra Divecha is senior product marketing manager at Cadence Design Systems

Dealing with parasitic-extraction challenges in finFETs and advanced nodes

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
July 25, 2014
Bundles help group signals on package pinouts

Multi-fabric planning for more efficient PCB design

A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.
June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
May 17, 2014
Real-number modeling signal resolution function

Real datatypes and tools enable fast mixed-signal simulation

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
March 19, 2014

Bring decaps under control with automated analysis

Decoupling capacitor counts are increasing as PCBs deploy more advanced silicon. But you can use automated analysis to bring counts and costs under control.
Article  |  Topics: PCB - Design Integrity, Layout & Routing  |  Tags: , ,   |  Organizations:
March 17, 2014
Chris Tice is corporate vice president and general manager of hardware system verification at Cadence Design Systems

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
January 21, 2014
Cadence Palladium cluster

Productivity, predictability and versatility drive verification environments

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
November 14, 2013
Cadence virtual prototyping

A map of the prototyping ecosystem

Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
Article  |  Topics: EDA - ESL, Verification  |  Tags: , , ,   |  Organizations:
November 11, 2013
Brian Fuller is editor in chief at Cadence Design Systems.

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
November 1, 2013
Jack Erickson is director of product management at Cadence Design Systems.

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Expert Insight  |  Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:


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