Cadence Design Systems

September 7, 2020
Ashish Darbari is CEO of formal verification consultancy and training provider Axiomise.

Everything you ever wanted to know about RISC-V architectural formal verification

But you were NOT afraid to ask.... It's time for some answers.
May 29, 2020
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

Covid-19 rings changes for virtual working

Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: , ,
March 15, 2019

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
July 22, 2016
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
May 23, 2016
Road signs used to train IDSIA neural network

Bit width tweaks point way to practical deep learning

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.
January 27, 2016
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
January 8, 2016
ESL options - thumbnail image

The shape of system design and verification in 2016

2016 marks the 20th anniversary of the term Electronic System Level (ESL), introduced by Gary Smith in 1996. Where are we now? And how will developments this year push the frontiers of practical ESL design?
Article  |  Topics: EDA - ESL  |  Tags: , , , ,   |  Organizations:
January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
December 17, 2015
USB Type C connector

Integrated IP supports cost-efficient USB Type-C

The arrival of USB Type C provides an opportunity for SoC design teams with opportunities to provide customers with significant cost savings. Integrated IP will help the process.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:

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