Cadence Design Systems

February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
July 22, 2016
Dr Lauro Rizzatti, verification consultant

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
May 23, 2016
Road signs used to train IDSIA neural network

Bit width tweaks point way to practical deep learning

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.
January 27, 2016
Dr Lauro Rizzatti, verification consultant

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
January 8, 2016
ESL options - thumbnail image

The shape of system design and verification in 2016

2016 marks the 20th anniversary of the term Electronic System Level (ESL), introduced by Gary Smith in 1996. Where are we now? And how will developments this year push the frontiers of practical ESL design?
Article  |  Topics: EDA - ESL  |  Tags: , , , ,   |  Organizations:
January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
December 17, 2015
USB Type C connector

Integrated IP supports cost-efficient USB Type-C

The arrival of USB Type C provides an opportunity for SoC design teams with opportunities to provide customers with significant cost savings. Integrated IP will help the process.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
November 26, 2015
Cadence mask coloring assistant

Mixed-signal designs prepare for coloring at 10nm

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
October 29, 2015
Innovus chip layout

Cadence’s path to digital implementation on 10nm

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
August 21, 2015
Visual: cars speeding along a road

Why emulation performance doesn’t matter (on its own)

Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors