Atrenta

August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
October 16, 2013
Piyush Sancheti, vice president of product marketing at Atrenta.

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:

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