Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
There’s already some love out there for ARM’s v8 64bit architecture as the processor giant builds out its ecosystem.
How do we bridge the gap between the highly abstract view provided by traditional system-level design and the detailed implementation in RTL? The article answers this question by describing the components within an ESL methodology and illustrating its use via customer case studies. The methodology uses the ARM RealView SoC Designer tool and Tenison Design […]
When microprocessor core developer ARM started in a barn outside Cambridge, England, just over fifteen years ago, odds were against it making a global impact. The team of “12 engineers and me”, as then CEO and now chairman Sir Robin Saxby puts it, “had no patents, a working prototype and £1.75m of cash.” Without the […]