Xilinx

March 19, 2018

Xilinx plans reconfigurable compute for 7nm FPGA generation

Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations:
February 25, 2018

55th DAC features design contest to build smarter drones

June's DAC will see the culmination of a contest involving more than 100 teams vying to demonstrate the best use of machine learning on embedded hardware in a flying drone.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations: ,
February 20, 2018

DVCon US 2018 preview: OneSpin Solutions

The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
September 12, 2017

Group to build CCIX accelerator test chip

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , , ,
February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
April 4, 2016

HyperLynx made broader and easier to use

HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
May 5, 2015

Xilinx updates Vivado with CDC, faster verification, third-party flows, and lab edition

New version of Vivado adds verification features and speed, extends Zynq support
Article  |  Topics: Product  |  Tags: ,   |  Organizations: , , , ,
August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,

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