Wilson Research Group


October 17, 2018

FPGA playing verification catch-up as bugs escape

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.

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