TSMC

June 18, 2018

DAC 2018 preview: Synopsys

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
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May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
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March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
September 12, 2017

Group to build CCIX accelerator test chip

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
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June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
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June 1, 2017

DAC 2017 preview: Synopsys

Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
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February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
January 18, 2017

Wafer expansion hits the buffers

What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
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May 18, 2016

ARM completes multicore test chip on 10nm finFET

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
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April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.

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