DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
New flow enables high-performance, high-integration designs.
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
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