Synopsys

May 5, 2015

Xilinx updates Vivado with CDC, faster verification, third-party flows, and lab edition

New version of Vivado adds verification features and speed, extends Zynq support
Article  |  Topics: Product  |  Tags: ,   |  Organizations: , , , ,
March 10, 2015

Synopsys claims finFET leadership

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
Article  |  Topics: Product  |  Tags:   |  Organizations: ,
February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
October 24, 2014

Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support

Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 14, 2014

ARC core focuses on embedded Linux applications

Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Article  |  Topics: Blog - IP, - Product  |  Tags: , , , ,   |  Organizations:
October 8, 2014

Still time to get to European design and verification conference

DVCon Europe brings design and verification insights to Munich next week.
October 1, 2014

Liberty changes bring together nanometer OCV techniques

The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
September 29, 2014

Verification platform offers unified compile, debug environments

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , , , , ,   |  Organizations:
September 29, 2014

TSMC adds sub-micron low-leakage processes

TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.
Article  |  Topics: Blog Topics  |  Tags: , , , , , ,   |  Organizations: , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors