Synopsys

November 5, 2013

Synopsys aims at fast real-time apps with ARC HS family

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
October 11, 2013

Verification Futures rolls out in Europe next month

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
September 12, 2013

SNUG heads to Austin next week

Synopsys user meet in Austin carries forward themes from Boston event.
Article  |  Topics: Conferences, Blog - EDA  |  Tags:   |  Organizations:
September 9, 2013

SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
September 5, 2013

SNUG Boston focuses on challenges of gigascale IC design

Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
Article  |  Topics: Conferences, Blog - EDA  |  Tags:   |  Organizations: , , , , ,
August 29, 2013

IP providers make plans for the internet of things

ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , , , , ,   |  Organizations: ,
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,
June 17, 2013

Synopsys doubles speed of formal ECO checking

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Article  |  Topics: Design to Silicon, RTL, Verification  |  Tags: ,   |  Organizations: ,
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,

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