Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
Synopsys user meet in Austin carries forward themes from Boston event.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
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