TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.
Building the internet of Things will demand collaboration and a healthy ecosystem
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
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