VCS AMS updates AMS verification tool and methodology
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
New data model and optimisation strategy, plus revised analysis engines update Synopsys's IC Compiler place and route tool
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
Uses improved logic optimisations and a new approach to meeting timing.
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
Synopsys user meet in Austin carries forward themes from Boston event.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
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