Synopsys

June 3, 2014

Synopsys adds formal, CDC, low-power checks to Verification Compiler

Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Article  |  Topics: Product, Verification  |  Tags: , ,   |  Organizations:
June 2, 2014

Chipmaking’s future: all of the nodes all of the time

The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
June 2, 2014

Samsung certifies Synopsys tools, IP at 14nm

Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Article  |  Topics: Conferences, Design to Silicon, Blog - IP  |  Tags: ,   |  Organizations: , ,
June 2, 2014

Synopsys uses virtual prototyping kits to kick start IP integration

Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations:
May 29, 2014

Synopsys adds vector DSP operations to ARC EM processor IP

Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
May 29, 2014
I heart DAC logo

IP takes center stage in push towards systems engineering

At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , , , , , ,
April 28, 2014

Synopsys speeds HAPS prototyping with ProtoCompiler

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype
Article  |  Topics: Blog Topics, RTL, Verification  |  Tags: , , , ,   |  Organizations:
April 16, 2014

FinFET variability issues challenge advantages of new process

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
March 28, 2014

Software quality acquisition to bring Synopsys “new friends”

Software quality testing company acquisition will broaden Synopsys's reach as well as serving current customers
Article  |  Topics: Verification  |  Tags: ,   |  Organizations:
March 26, 2014

Better Software, Faster!: free virtual prototyping book available now

Free book explains virtual prototyping and includes case studies about virtual prototyping from Altera, Bosch, GM, Hitachi, Lauterbach, Linaro, Microsoft, Renesas, Ricoh, Siemens, and TI.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations: , , , , , , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors