Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
Synopsys develops portfolio of ASIL B ready IP, and invests in AEC-Q100 testing and TS 16949 quality management, to ease automotive SoC qualification.
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Synopsys will be emphasising its 'silicon to software' offering at the 2015 Design Automation Conference.
Conference addresses formal verification techniques at levels to suit beginners through to experts
Benchmarking organization EEMBC has kicked off an effort to develop a set of performance tests for edge nodes for the Internet of Things (IoT).
New version of Vivado adds verification features and speed, extends Zynq support
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