A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Synopsys has introduced TetraMAX II, a faster and more parallelisable ATPG and diagnostics solution, which is now also certified for use in ISO 26262 compliant automotive designs.
Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
Do the synapses in the human brain offer a new model for the design flow in a Smart Everything world?
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
Synopsys is updating its custom design tools to make working with finFET based processes easier.
Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.
A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
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