Synopsys will be emphasising its 'silicon to software' offering at the 2015 Design Automation Conference.
Conference addresses formal verification techniques at levels to suit beginners through to experts
Benchmarking organization EEMBC has kicked off an effort to develop a set of performance tests for edge nodes for the Internet of Things (IoT).
New version of Vivado adds verification features and speed, extends Zynq support
Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
DVCon Europe brings design and verification insights to Munich next week.
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