Synopsys

October 17, 2017

Arm TechCon 2017 preview: Synopsys

Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
June 20, 2017

Formal focus for Synopsys blog

Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
Article  |  Topics: Industry Blogs, Verification  |  Tags: , , ,   |  Organizations:
June 14, 2017

DAC 2017 preview: ESD Alliance

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: ,   |  Organizations: , , , , , , , ,
June 1, 2017

DAC 2017 preview: Synopsys

Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
Article  |  Topics: Conferences  |  Tags:   |  Organizations: , , , , , ,
April 13, 2017

DVCon China looms as submission deadline for Europe approaches

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
March 24, 2017

The return of the CEO Outlook

The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
February 15, 2017

DVCon US 2017 preview: Mentor Graphics

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
February 1, 2017

Five steps to faster FPGA implementation

Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
Article  |  Topics: Design to Silicon  |  Tags: , ,   |  Organizations:
January 10, 2017

Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation

Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
Article  |  Topics: ESL/SystemC, Product  |  Tags: , ,   |  Organizations:

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