Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolle.
Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
IP provides key building blocks for building better video and audio playback devices using HDMI 2.1
Better integration of EM modeling and analysis tools with Synopsys' Custom Compiler should enable tighter design margins
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
Will discuss how automotive OEMs and chip designers can use AI, deep learning, and convolutional neural networks to achieve better performance than traditional techniques.
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
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