The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
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