Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
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