Standards

April 17, 2023

Semidynamics pushes configurability on RISC-V core for HPC

Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
April 17, 2023

DVCon Europe adds research track

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
March 30, 2023

SEMI predicts strong 300mm growth to 2026

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
January 18, 2023

Accellera forms CDC working group and takes security standard to IEEE

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
January 6, 2023

DVCon Europe best paper speeds up memory-controller tests

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: ,
November 21, 2022

DVCon Europe looks to network effects

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations:
October 25, 2022

DVCon Europe keynotes focus on connectivity

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022

Accellera attempts to standardize CDC data

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Article  |  Topics: Blog Topics, Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.

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