Emulation’s scheduling challenge
Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
SiFive
Siemens brings chip-design flow to DARPA Toolbox Initiative
Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.
Getting a RISC-V embedded toolchain in place
A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
RISC-V in nearly a quarter of designs (Wilson Functional Verification 2020 – Part One)
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
Breker adds automated system integration test generation for RISC-V
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
RISC-V firms aim for lower-cost design starts
Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
Netronome launches chiplet initiative for network-accelerator SIPs
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
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