Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
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