Packaging


November 20, 2023

ETRI builds flow for AI chiplets

South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Article  |  Topics: Blog - EDA, - HPC, Next Generation Design, Packaging, Verification  |  Tags: , , ,   |  Organizations: , ,
June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations: ,
November 4, 2013

Amkor keeps question mark next to ‘full’ 3D-IC in 2016

Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
October 23, 2013

3D-IC focus for GSA’s Taipei Memory+ event next week

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.

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