Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Review highlights from Mentor's activities at DAC and grab your last chance to register for in-depth technical sessions.
Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.
Conference addresses formal verification techniques at levels to suit beginners through to experts
New version of Vivado adds verification features and speed, extends Zynq support
Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
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