Mentor Graphics

May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
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May 22, 2013

Mentor adds rapid RFQ to Capital suite

Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.
Article  |  Topics: Blog - PCB  |  Tags:   |  Organizations:
May 21, 2013

Aldec automates safety-critical traceability

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.
May 14, 2013

DAC 2013 Preview VI: CEO ‘visions’ added

Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.
April 10, 2013

FinFET father headlines Mentor’s west coast user conference

Dr Chenming Hu joins Mentor CEO Wally Rhines and Xilinx SVP Victor Peng to keynote free day-long User2User in San Jose on April 25th, capping a full technical program.
Article  |  Topics: Conferences, Blog - EDA, Embedded, PCB  |  Tags:   |  Organizations: , ,
March 18, 2013

Flotherm release moves thermal planning to concept stage

Mentor Graphics has release a version of its Flotherm tool that makes it possible to build accurate models of heat flow through electronic systems from initial concepts through to prototypes without the extensive manual rework that these analyses have needed traditionally.
Article  |  Topics: Blog - PCB  |  Tags: ,   |  Organizations:
January 30, 2013

Mentor updates HyperLynx for faster boards, more rules checking

Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
December 5, 2012

IPSoC: Software power optimization ‘must start earlier’

Embedded software engineers need to focus on power optimization in their code much earlier and more comprehensively than many of them do today, says Mentor Graphics technologist Colin Walls.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations:
November 19, 2012

‘Process and metrics before tools for better verification’

Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Article  |  Topics: Blog Topics, Blog - EDA, - Industry Blogs, Tested Component to System, Verification  |  Tags: , ,   |  Organizations: ,

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