The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
Registration is free-of-charge to attend Mentor, Oracle and Samsung keynotes and choose from nine technical tracks at one-day event.
Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
Valor additions aim to deliver shopfloor data to PCB ERP systems in real time... for the first time. And could boost ROI beyond 70%.
Mentor's new version of its RTOS targets once high-cost flexibility with secure and reliable in-operation upgrades and app swap-outs for medical, industrial and smart energy.
View All Sponsors