Mentor Graphics

June 14, 2017

DAC 2017 preview: ESD Alliance

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: ,   |  Organizations: , , , , , , , ,
June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations: ,
June 1, 2017

DAC 2017 preview: Mentor

Mentor, a Siemens business, has released details on its varied activities at DAC 2017, ranging from panels to technical papers.
Article  |  Topics: Blog Topics  |  Tags: ,   |  Organizations: , , ,
May 30, 2017

How Mentor realized concurrent engineering for PCB design

The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
May 12, 2017

Toshiba case study describes advanced thermal simulation

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.
May 3, 2017

Master the verification challenge of PCIe-based NVMe storage

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , , ,   |  Organizations: ,
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
April 13, 2017

DVCon China looms as submission deadline for Europe approaches

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
April 6, 2017

Leverage AI and centralized processing for L-5 autonomous vehicles

L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.
April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.

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