Mentor Graphics

June 10, 2016

DFT to expand its role for long-term yield

Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
June 6, 2016

ARM recruits design houses and tools for quicker IoT projects

ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , ,
June 1, 2016

Samsung taps Mentor for Closed-Loop DFM

Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
May 25, 2016

DAC 2016 preview: Mentor Graphics

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
May 23, 2016

Mentor integrates automotive IGBT test and simulation

A new dedicated automotive power tester helps cut simulation errors to just 0.5% with more faithful calibration.
April 20, 2016

Toward easier, faster test pattern simulation

Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.
Article  |  Topics: Blog - EDA, - Tested Component to System, Verification  |  Tags: , , , , ,   |  Organizations:
April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
April 4, 2016

HyperLynx made broader and easier to use

HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.

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