Mentor Graphics

April 13, 2017

DVCon China looms as submission deadline for Europe approaches

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
April 6, 2017

Leverage AI and centralized processing for L-5 autonomous vehicles

L-5 autonomous vehicles need centralized raw data analysis with machine learning to cope with the demands of ASIL-D functional safety. Mentor's response is DRS360.
April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
March 31, 2017

Combining 1D and 3D CFD simulation for piping systems

Computational fluid dynamics now addresses more of the simulation activities required for complex systems in a single methodology.
March 24, 2017

The return of the CEO Outlook

The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
March 23, 2017

Leverage a zero-cost proof-of-concept platform for the IoT

ARM and Tanner EDA aim to chart a path toward cheaper, easier to realize designs for the embedded and Internet-of-Things markets.
March 7, 2017

Reducing the documentation burden in ISO 26262

The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
March 6, 2017

Mentor’s Xpedition virtualizes simulation for ruggedized, safety-critical designs

Xpedition adds vibration and acceleration analysis to shorten physical PCB test times for ruggedized and safety-critical designs.
March 6, 2017

Embedded World 2017 preview: Mentor Graphics

Three Mentor divisions - Embedded, PADS and Tanner EDA - will present their latest innovations during the conference and exhibition in Nuremberg next week.
Article  |  Topics: Blog - EDA, Embedded, PCB  |  Tags: , , , , , , , ,   |  Organizations: , ,
March 2, 2017

How formal concentrates ISO 26262 fault analysis

Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors