Leaders from Cadence, Jasper, Mentor and Synopsys are late additions to DAC 2013, giving 15-minute pre-keynote talks previewing design's next half century.
Dr Chenming Hu joins Mentor CEO Wally Rhines and Xilinx SVP Victor Peng to keynote free day-long User2User in San Jose on April 25th, capping a full technical program.
Mentor Graphics has release a version of its Flotherm tool that makes it possible to build accurate models of heat flow through electronic systems from initial concepts through to prototypes without the extensive manual rework that these analyses have needed traditionally.
Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Embedded software engineers need to focus on power optimization in their code much earlier and more comprehensively than many of them do today, says Mentor Graphics technologist Colin Walls.
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
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