IMEC

October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
December 7, 2016

IMEC stacks nanowire transistors together on CMOS

IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: , ,
October 9, 2015

IMEC 5nm test chip to explore EUV and SAQP litho options

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,
October 28, 2014

imec and Coventor partner for 7nm process development

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
Article  |  Topics: Design to Silicon  |  Tags: , , , ,   |  Organizations: ,
September 11, 2014

TSMC: e-beam winning on cost over EUV for lithography

EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,
March 26, 2014

Even EUV faces a 1D future, says IMEC

IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
November 20, 2013

FinFETs’ III-V future promises sub-7nm, RF and opto CMOS

FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations:
March 22, 2013

DATE: Silicon Europe plans to build cluster of clusters

Four of the European centers for electronics research and business development have set up a project to try to create a virtual “silicon cluster” that aims ultimately to build a worldwide development network for energy-efficient systems.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors