IMEC

June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
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June 18, 2018

Switch to orbit mode boosts MRAM on 300mm wafers

Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
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May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
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May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
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May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
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February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
December 6, 2017

European teams explore 3D integration tradeoffs

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
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October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
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December 7, 2016

IMEC stacks nanowire transistors together on CMOS

IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
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December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
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