IEEE


June 25, 2014

Accellera releases version 1.2 of UVM

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
June 3, 2013

UPF group moves to consider system-power issues

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 30, 2013

Latest version of IEEE 1801/UPF available for free

The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
December 18, 2012

DATE conference prepares program for March

In 2013, the Design Automation and Test in Europe (DATE) conference returns to Grenoble, France and with focus days on the Internet of Things and the cloud.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
November 27, 2012

Cadence gears up for automotive switch to ethernet

Cadence Design Systems has developed semiconductor IP for the automotive industry's OPEN Alliance to make ethernet the core networking backbone of future motor vehicles.
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Article  |  Topics: Blog Topics, Blog - EDA, - Industry Blogs, Tested Component to System, Verification  |  Tags: , ,   |  Organizations: ,
October 25, 2012

Ambipolar FETs are an each-way bet

Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
Article  |  Topics: Blog Topics, Commentary, Conferences  |  Tags: ,   |  Organizations: ,

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