March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
June 16, 2015

Collaboration let HiSilicon accelerate 16nm finFET plans

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
March 10, 2015

Synopsys claims finFET leadership

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
Article  |  Topics: Product  |  Tags:   |  Organizations: ,
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
October 25, 2012

Using verification IP to master AMBA and wider protocol proliferation

How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Article  |  Topics: Blog Topics, Commentary, Blog - EDA, - Standards, Verification  |  Tags: ,   |  Organizations: , , ,


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors