GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
GlobalFoundries intends to offer a 12nm FinFET process as a stepping stone from its 14nm process.
Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
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