Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
Local EDA vendor Austemper will be demonstrating a comprehensive functional safety design tool suite in Austin next week.
At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.
Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.
EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
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