The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.
Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
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