CEA-Leti

October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
December 15, 2015

GaN power makes progress at IEDM 2015

Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , ,   |  Organizations: ,
June 8, 2015

CEA-Leti adds partners to FD-SOI low-power design centre

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , ,
March 12, 2015

Cea-Leti opens FD-SOI design center

CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
March 11, 2015

IoT and RF ‘to drive FD-SOI adoption’

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations: , ,
March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
March 27, 2013

Intel and ST stake claims to foundry low power designs

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.

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