Cadence Design Systems

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.

Cadence Design Systems has made three additions to its OrCAD line of PCB tools, largely aimed at data management and organization for projects.

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.

Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.

Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.