Cadence Design Systems

June 14, 2017

DAC 2017 preview: ESD Alliance

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: ,   |  Organizations: , , , , , , , ,
May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations:
May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
May 17, 2017

Matlab links up with Virtuoso for circuit analytics

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.
May 16, 2017

Cadence adapts Jasper tools for CDC and lint

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations:
May 11, 2017

Racyics puts FD-SOI design flow online

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: , ,
May 1, 2017

Cadence tunes fixed-point DSP for neural networks

Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
April 12, 2017

Cadence cuts up DRC for speed

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
March 24, 2017

The return of the CEO Outlook

The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
March 7, 2017

POSTPONED: Get to grips with new PC, monitor energy regs

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Article  |  Topics: Blog - EDA, - Standards  |  Tags:   |  Organizations: , , , , , ,

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