Cadence Design Systems

April 12, 2017

Cadence cuts up DRC for speed

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
March 24, 2017

The return of the CEO Outlook

The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
March 7, 2017

POSTPONED: Get to grips with new PC, monitor energy regs

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Article  |  Topics: Blog - EDA, - Standards  |  Tags:   |  Organizations: , , , , , ,
February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
February 15, 2017

DVCon US 2017 preview: Mentor Graphics

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
November 15, 2016

Siemens agrees deal to buy Mentor Graphics

German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
October 26, 2016

Cadence maps out safety plan for semiconductor-design tools

Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
August 24, 2016

Cadence building photonics environment around Virtuoso

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , ,   |  Organizations:
July 26, 2016

Cadence adds floating point to Fusion

Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , ,   |  Organizations:

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