Cadence Design Systems

May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 9, 2018

Motion harvester wins MEMS design contest

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
May 8, 2018

Cadence opens three fronts on mixed-signal failures

Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
April 11, 2018

Tensilica DSP extends pipeline for performance

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
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April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
September 12, 2017

Group to build CCIX accelerator test chip

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , , ,
June 14, 2017

DAC 2017 preview: ESD Alliance

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: ,   |  Organizations: , , , , , , , ,
May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations:
May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
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